Electronic assembly with high capacity thermal interface and methods of manufacture

ABSTRACT

To accommodate high power densities associated with high performance integrated circuits, an integrated circuit package includes a heat-dissipating structure in which heat is dissipated from a surface of one or more dice to an integrated heat spreader (IHS) through a high capacity thermal interface formed of diamond, a diamond composite, or graphite. In one embodiment, a diamond layer is grown on the IHS. In another embodiment, a diamond layer is separately formed and affixed to the IHS. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

TECHNICAL FIELD OF THE INVENTION

[0001] The present invention relates generally to electronics packaging.More particularly, the present invention relates to an electronicassembly that includes an integrated circuit package comprising a highcapacity thermal interface between the integrated circuit and a heatspreader to dissipate heat generated in a high performance integratedcircuit, and to manufacturing methods related thereto.

BACKGROUND OF THE INVENTION

[0002] Integrated circuits (IC's) are typically assembled into packagesby physically and electrically coupling them to a substrate made oforganic or ceramic material. One or more IC packages can be physicallyand electrically coupled to a printed circuit board (PCB) to form an“electronic assembly”. The “electronic assembly” can be part of an“electronic system”. An “electronic system” is broadly defined herein asany product comprising an “electronic assembly”. Examples of electronicsystems include computers (e.g., desktop, laptop, hand-held, server,etc.), wireless communications devices (e.g., cellular phones, cordlessphones, pagers, etc.), computer-related peripherals (e.g., printers,scanners, monitors, etc.), entertainment devices (e.g., televisions,radios, stereos, tape and compact disc players, video cassetterecorders, MP3 (Motion Picture Experts Group, Audio Layer 3) players,etc.), and the like.

[0003] In the field of electronic systems there is an incessantcompetitive pressure among manufacturers to drive the performance oftheir equipment up while driving down production costs. This isparticularly true regarding the packaging of IC's on substrates, whereeach new generation of packaging must provide increased performance,particularly in terms of an increased number of components and higherclock frequencies, while generally being smaller or more compact insize. As the density and clock frequency of IC's increase, theyaccordingly generate a greater amount of heat. However, the performanceand reliability of IC's are known to diminish as the temperature towhich they are subjected increases, so it becomes increasingly importantto adequately dissipate heat from IC environments, including ICpackages.

[0004] An IC substrate may comprise a number of metal layers selectivelypatterned to provide metal interconnect lines (referred to herein as“traces”), and one or more electronic components mounted on one or moresurfaces of the substrate. The electronic component or components arefunctionally connected to other elements of an electronic system througha hierarchy of electrically conductive paths that include the substratetraces. The substrate traces typically carry signals that aretransmitted between the electronic components, such as IC's, of thesystem. Some IC's have a relatively large number of input/output (I/O)terminals (also called “lands”), as well as a large number of power andground terminals or lands.

[0005] As the internal circuitry of IC's, such as processors, operatesat higher and higher clock frequencies, and as IC's operate at higherand higher power levels, the amount of heat generated by such IC's canincrease their operating temperature to unacceptable levels.

[0006] For the reasons stated above, and for other reasons stated belowwhich will become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a significant need inthe art for apparatus and methods for packaging an IC on a substratethat minimize heat dissipation problems associated with high clockfrequencies and high power densities.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007]FIG. 1 is a block diagram of an electronic system incorporating atleast one electronic assembly with a high capacity thermal interface inaccordance with one embodiment of the invention;

[0008]FIG. 2 illustrates a cross-sectional representation of a prior artIC package;

[0009]FIG. 3 illustrates a cross-sectional representation of anelectronic assembly comprising an IC package with a high capacitythermal interface, in accordance with one embodiment of the invention;

[0010]FIG. 4 illustrates a cross-sectional representation of anelectronic assembly comprising a multi-chip IC package with a highcapacity thermal interface, in accordance with another embodiment of theinvention;

[0011]FIG. 5 illustrates a cross-sectional representation of a highcapacity thermal interface formed on an integrated heat spreader, inaccordance with one embodiment of the invention;

[0012]FIG. 6 illustrates a cross-sectional representation of a highcapacity thermal interface to be affixed to an integrated heat spreader,in accordance with another embodiment of the invention;

[0013]FIG. 7 is a view of a wafer of diamond thermal interface material,which has been grown separate from an IHS, and a segment thereof priorto attachment to an IHS, in accordance with another embodiment of theinvention;

[0014]FIG. 8 is a flow diagram of a method of fabricating an IC package,in accordance with one embodiment of the invention; and

[0015]FIG. 9 is a flow diagram of two alternative methods of affixing alayer of thermally conductive material to an integrated heat spreader(IHS).

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

[0016] In the following detailed description of embodiments of theinvention, reference is made to the accompanying drawings which form apart hereof, and in which is shown by way of illustration specificpreferred embodiments in which the inventions may be practiced. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention, and it is to be understood thatother embodiments may be utilized and that structural, mechanical,compositional, and electrical changes may be made without departing fromthe spirit and scope of the present inventions. The following detaileddescription is, therefore, not to be taken in a limiting sense, and thescope of the present invention is defined only by the appended claims.

[0017] The present invention provides a solution to thermal dissipationproblems that are associated with prior art packaging of integratedcircuits that have high circuit density and that operate at high clockspeeds and high power levels, by employing a high capacity thermalmaterial as a thermal interface between one or more IC's and a heatspreader. Various embodiments are illustrated and described herein.

[0018] In one embodiment, a front surface of an IC die is flip-chipmounted to an organic land grid array (OLGA) substrate using “controlledcollapse chip connect” (C4) technology. A high capacity thermalinterface material is attached between the back surface of the die andan integrated heat spreader (IHS) after suitable preparation of the dieand IHS surfaces. In one embodiment, the high capacity thermal materialcomprises diamond, a diamond composite, or graphite. A side wall of theIHS can also be coupled to the OLGA substrate around the die peripherywith a suitable thermal sealant in order to provide further heatdissipation as well as mechanical strength.

[0019]FIG. 1 is a block diagram of an electronic system 1 incorporatingat least one electronic assembly 4 with a high capacity thermalinterface in accordance with one embodiment of the invention. Electronicsystem 1 is merely one example of an electronic system in which thepresent invention can be used. In this example, electronic system 1comprises a data processing system that includes a system bus 2 tocouple the various components of the system. System bus 2 providescommunications links among the various components of the electronicsystem 1 and can be implemented as a single bus, as a combination ofbusses, or in any other suitable manner.

[0020] Electronic assembly 4 is coupled to system bus 2. Electronicassembly 4 can include any circuit or combination of circuits. In oneembodiment, electronic assembly 4 includes a processor 6 which can be ofany type. As used herein, “processor” means any type of computationalcircuit, such as but not limited to a microprocessor, a microcontroller,a complex instruction set computing (CISC) microprocessor, a reducedinstruction set computing (RISC) microprocessor, a very long instructionword (VLIW) microprocessor, a graphics processor, a digital signalprocessor (DSP), or any other type of processor or processing circuit.

[0021] Other types of circuits that can be included in electronicassembly 4 are a custom circuit, an application-specific integratedcircuit (ASIC), or the like, such as, for example, one or more circuits(such as a communications circuit 7) for use in wireless devices likecellular telephones, pagers, portable computers, two-way radios, andsimilar electronic systems. The IC can perform any other type offunction.

[0022] Electronic system 1 can also include an external memory 10, whichin turn can include one or more memory elements suitable to theparticular application, such as a main memory 12 in the form of randomaccess memory (RAM), one or more hard drives 14, and/or one or moredrives that handle removable media 16 such as floppy diskettes, compactdisks (CDs), digital video disk (DVD), and the like.

[0023] Electronic system 1 can also include a display device 8, one ormore speakers 9, and a keyboard and/or controller 20, which can includea mouse, trackball, game controller, voice-recognition device, or anyother device that permits a system user to input information into andreceive information from the electronic system 1.

[0024]FIG. 2 illustrates a cross-sectional representation of a prior artIC package 30. IC package 30 represents a typical prior art structurethat includes an IC die 40 mounted in “flip-chip” orientation with itslands (not shown) facing downward to couple with corresponding lands 52on the upper surface of a substrate 50 through solder balls or bumps 42.Substrate 50 can be a one-layer board or a multi-layer board, and it caninclude additional lands 54 on its opposite surface for mating withadditional packaging structure (not shown).

[0025] Die 40 generates its heat from internal structure, includingwiring traces, that is located near its lower surface; however, most ofthe heat is dissipated through its upper surface. Heat that isconcentrated within die 40 is dissipated to a large surface that is incontact with die 40 in the form of a heat spreader 60 that is typicallyformed of metal such as copper or aluminum. To improve the thermalconductivity between die 40 and the heat spreader 60, a thermalinterface material 70 is often provided between die 40 and heat spreader60. The thermal interface material 70 typically is a thermal gel orgrease containing metal particles.

[0026] To further dissipate heat from heat spreader 60, a heat sink 80optionally having heat fins 82 is often coupled to heat spreader 60.Heat sink 80 dissipates heat into the ambient environment.

[0027] An increase in the junction temperature T_(j) of an electronicdevice on the IC can adversely affect the operating lives of the device.Junction temperature is a function of three factors: junction-to-ambientthermal resistance, power dissipation, and ambient temperature. T_(j)can be expressed by Equation 1:

T _(j)=(θ_(ja) ×P _(d))+T _(a)  (Equation 1)

[0028] wherein

[0029] T_(j)=junction temperature (in degrees C.);

[0030] θ_(ja)=the junction-to-ambient thermal resistance (in degreesC./watt);

[0031] P_(d)=power dissipation at T_(j) (in watts); and

[0032] T_(a)=ambient temperature (in degrees C.).

[0033] The junction-to-ambient thermal resistance θ_(ja) can berepresented by Equation 2:

θ_(ja)=θ_(jc)+θ_(cs)+θ_(sa)  Equation 2)

[0034] wherein

[0035] θ_(jc)=the junction-to-case thermal resistance (in degreesC./watt);

[0036] O_(cs)=the case-to-sink thermal resistance (in degrees C./watt);and

[0037] θ_(sa)=the sink-to-ambient thermal resistance (in degreesC./watt);

[0038] In the foregoing definitions, the pertinent location of the caseis the top center of the IC package, including any IHS forming part ofthe IC package. The pertinent location of the sink can be the geometriccenter of the heat sink.

[0039] The IC package 30 of FIG. 2 is for most purposes no longercapable of meeting the thermal-dissipating requirements of today's highperformance electronic assemblies, as expressed in terms of thejunction-to-ambient thermal resistance θ_(ja).

[0040] The present invention reduces the device junction temperatureT_(j) by reducing both the junction-to-case thermal resistance θ_(jc)and the case-to-sink thermal resistance θ_(cs). Processor assemblies forhigh performance servers have a very nonuniform power map or heat fluxvariation across the surfaces of the die. In a 3D thermal mapping, thehot spots appear as mountain peaks across the upper die surface, forexample. It is the temperature of the highest flux area(s) thattypically must be maintained at or below a specified value. While thesilicon die provides some lateral heat spreading, it is insufficient toappreciably reduce the peak temperature(s).

[0041] Even the high thermal conductivity of copper (which is greaterthan three times that of silicon) is insufficient to handle the hotspots. If existing thermal dissipation structure is incapable ofdissipating sufficient heat to maintain the die peak temperature below aspecified value, the performance of the electronic assembly must bethrottled back by reverting to a temperature-dependent processor powercontrol process. Otherwise, the electronic assembly could malfunction orexperience a catastrophic failure. Thus, with increased heat dissipationrequirements for electronic assemblies, it has become necessary tosubstantially improve the performance of thermal interface materials andintegrated heat spreaders.

[0042]FIG. 3 illustrates a cross-sectional representation of anelectronic assembly 100 comprising an IC package with a high capacitythermal interface 110, in accordance with one embodiment of theinvention. The IC package comprises a die 40 mounted on an organic landgrid array (OLGA) substrate 50, and an integrated heat spreader (IHS)120. While an OLGA substrate is shown, the present invention is notlimited to use with an OLGA substrate, and any other type of substratecan be employed. The IC package illustrated in FIG. 3 can form part ofelectronic assembly 4 shown in FIG. 1. Die 40 can be of any type. In oneembodiment, die 40 is a processor.

[0043] In FIG. 3, die 40 comprises a plurality of signal conductors (notshown) that terminate in electrical contacts or lands on the bottomsurface (not shown) of die 40. These lands can be coupled tocorresponding electrical contacts or lands 52 representing signal,power, or ground nodes on the upper surface 56 of OLGA substrate 50 byappropriate connections such as C4 solder bumps 42. A suitable underfill(not shown), such as an epoxy material, can be used to surround C4solder bumps 42 to provide mechanical stability and strength.

[0044] Still referring to FIG. 3, an integrated heat spreader (IHS) 120forms a cover over die 40. IHS 120 is thermally coupled to an uppersurface of die 40 through a high capacity thermal interface 110. Die 40can thus dissipate a substantial amount of heat both laterally andvertically through thermal interface 110 to IHS 120.

[0045] Thermal interface 110 comprises a material that is capable ofconducting heat at a high rate. In one embodiment, thermal interface 110comprises diamond. A layer of thermal interface 110 comprising diamondhas a very high thermal conductivity in all directions within the layer.In other embodiments, thermal interface 110 can comprise other materialswith thermal qualities that are only slightly inferior to diamond, suchas a diamond composite, or graphite. A suitable diamond composite cancomprise a mixture of diamond particles and particles of anothersubstance, such as aluminum or copper. While graphite is an excellentthermal conductor within a given plane of graphite material, it is not agood thermal conductor in a direction that is normal to a plane.However, graphite may suffice for applications that do not requireoptimal thermal dissipation.

[0046] IHS 120 includes a lid 122 and a side wall or support member 124.Thermal interface 110 is in contact with the lower surface 58 of lid 122and with the upper surface of die 40. In one embodiment, thermalinterface 110 is affixed to die 40 and/or to lid 122.

[0047] Thermal interface 110 can be formed in at least two differentways. For example, thermal interface 110 can be formed by growing it onthe lower surface 58 of lid 122, as explained further regarding FIG. 5.Alternatively, thermal interface 110 can be formed apart from IHS 120and subsequently affixed to lid 122 of IHS 120, as explained furtherregarding FIGS. 6 and 7.

[0048] In one embodiment, thermal interface 110 has a surface area thatis substantially the same as the bottom surface area of lid 122. Asviewed, for example, in FIG. 3, thermal interface 110 coverssubstantially the entire bottom surface of lid 122. Thermal interface110 can extend laterally to be in contact with support member 124.

[0049] IHS 120 can be mechanically supported by coupling its supportmember 124 to the upper surface 56 of OLGA substrate 50 through asuitable sealant 66. In one embodiment, the support member 124 islocated at the periphery of IHS 120. However, in other embodiments thelid 122 of IHS 120 can extend beyond the support member 124.

[0050] Sealant 66 can comprise a thermally conductive material such as athermal grease or gel, or a heat-curable material such as athermo-setting resin or epoxy. The thermally conductive material cancomprise particles of metal or other thermally conductive substance(s).

[0051] To further increase the rate of heat dissipation from IHS 120, aheat sink 80 of any suitable shape (including optional heat fins 82),material, and size can optionally be coupled to or formed as part of theupper surface of the lid 122 of IHS 120.

[0052] OLGA substrate 50 can be of any type, including a multi-layersubstrate. OLGA substrate 50 can be mounted to an additional substrate130, such as a printed circuit board (PCB) or card. OLGA substrate 50can comprise, for example, a plurality of lands 126 that can bemechanically and electrically coupled to corresponding lands 128 ofsubstrate 130 by suitable connectors such as ball grid array (BGA)solder balls 127.

[0053] While a BGA arrangement 125 is illustrated in FIG. 3 for couplingOLGA substrate 50 to substrate 130, the present invention is not limitedto use with a BGA arrangement, and it can be used with any other type ofpackaging technology. Further, the present invention is not to beconstrued as limited to use in C4 packages, and it can be used with anyother type of IC package where the herein-described features of thepresent invention provide an advantage.

[0054]FIG. 4 illustrates a cross-sectional representation of anelectronic assembly 200 comprising a multi-chip IC package with a highcapacity thermal interface, in accordance with another embodiment of theinvention. While the embodiment shown in FIG. 3 has been described withreference to a single IC device, the invention is not limited topackaging single IC's and can be used for packaging multiple IC's. Oneexample is the multi-chip IC package or multi-chip module shown in FIG.4.

[0055] Electronic assembly 200 comprises a plurality of IC's in the formof dice 241-244, which are mounted to lands 252 on an upper surface 256of substrate 250 (which can be an OLGA substrate) via correspondingsolder balls or bumps 253. While an OLGA substrate is shown, theinvention is not limited to use with an OLGA substrate, and any othertype of substrate can be employed. The multi-chip module illustrated inFIG. 4 can form part of electronic assembly 4 shown in FIG. 1. Dice241-244 can be of any type. In one embodiment, die 243 is a processor.

[0056] Certain ones of dice 241-244 are high heat producers, and theyare coupled to IHS 220 through corresponding high capacity thermalinterfaces. For example, dice 241 and 243 generate high thermal outputsand are thermally coupled to the under side 258 of IHS 220 through highcapacity thermal interfaces 205 and 210, respectively. Normally, thethermal interface is wider than the die, as exemplified by thermalinterface 205. However, the width of the thermal interface canalternatively be the same as or smaller than the width of the die, asexemplified by thermal interface 210. Moreover, the dimensions of thethermal interface can be tailored to the die hot spots. For example, oneor more thermal interfaces can be positioned over a corresponding numberof die hot spots.

[0057] IHS 220 includes a lid 222 and a side wall or support member 224.Thermal interfaces 205 and 210 are in contact with the lower surface 258of lid 222 and with the upper surfaces of dice 241 and 243,respectively.

[0058] IHS 220 can be mechanically secured by coupling its supportmember 224 to the upper surface 256 of OLGA substrate 250 through asuitable sealant 266. As mentioned regarding FIG. 3, the support member224 is shown located at the periphery of IHS 220; however, in otherembodiments the lid 222 of IHS 220 can extend beyond the support member224. To further increase the rate of heat dissipation from IHS 220, aheat sink (not shown) of any suitable shape, material, and size canoptionally be coupled to or formed as part of the upper surface of thelid 222 of IHS 220.

[0059] OLGA substrate 250 can be of any type, including a multi-layersubstrate. OLGA substrate 250 can be mounted to an additional substrate230, such as a printed circuit board (PCB) or card. OLGA substrate 250can comprise, for example, a plurality of lands 226 that can bemechanically and electrically coupled to corresponding lands 228 ofsubstrate 230 by suitable connectors such as ball grid array (BGA)solder balls 227.

[0060] While a BGA arrangement 225 is illustrated in FIG. 4 for couplingOLGA substrate 250 to substrate 230, the present invention is notlimited to use with a BGA arrangement, and it can be used with any othertype of packaging technology. Further, the present invention is not tobe construed as limited to use in C4 packages, and it can be used withany other type of IC package where the herein-described features of thepresent invention provide an advantage.

[0061] While in the embodiment shown in FIG. 4, individual thermalinterfaces, such as thermal interfaces 205 and 210, have been providedfor only certain dice, such as dice 241 and 243, in another embodimentof a multi-chip module, a continuous thermal interface layer could beprovided between all of the dice 241 244 and the lid 222 of IHS 220.Such a thermal interface could have a surface area that is substantiallycoextensive with the bottom surface area of lid 222.

[0062] The fabrication of an IC package comprising a high capacitythermal interface will now be described.

Fabrication

[0063] In order to successfully fabricate an IC package with theadvantages described above, it is necessary to form a layer of highcapacity thermal interface material, such as diamond. It is alsoimportant to affix the high capacity thermal interface securely to theunder side of IHS as well as to the top side of the die. To do sorequires a die surface that is readily solderable. In an embodimentwherein the thermal interface is grown apart from the IHS, it is alsoimportant to have an IHS that is readily solderable. It is alsodesirable to provide at least one solderable surface on the thermalinterface. Each of the above-mentioned factors will now be described insufficient detail to enable one of ordinary skill in the art tounderstand and practice the invention.

[0064]FIG. 5 illustrates a cross-sectional representation of a highcapacity thermal interface 110 formed on an IHS 120, in accordance withone embodiment of the invention. As mentioned earlier, thermal interface110 (FIGS. 3 and 5) can be formed by growing it on the under surface 58of lid 122. In one embodiment, a layer of amorphous or polycrystallinediamond is grown on surface 58 using suitable chemical depositionmethods, such as chemical vapor deposition (CVD). Generally,polycrystalline diamond is preferred to amorphous diamond, because theformer has superior heat-dissipating characteristics.

[0065] In order to grow a diamond layer on a bare (unplated) surface 58of lid 122 of IHS 120, one or more adhesion layers 131-133 of a suitablematerial must first be affixed to surface 58. It is assumed that IHS 120is formed of copper in this example, but it can be formed of differentmaterials than copper.

[0066] The one or more adhesion layers 131-133 can comprise metal from agroup that includes chromium, gold, nickel, platinum, silver, titanium,tungsten, and vanadium, or alloys thereof. Because diamond that is grownthrough a CVD process adheres well to titanium, titanium is generallyused for layers that are in contact with diamond. However, tungstencould be substituted for titanium.

[0067] A layer 131 of nickel is first formed on surface 58 of lid 122.

[0068] Next a layer 132 of nickel-vanadium is formed on layer 131.Either platinum or chromium could be substituted for nickel-vanadium.

[0069] Next a layer 133 of titanium is formed on layer 132.

[0070] Next a thermal interface layer 110 of diamond material is formed,for example using CVD, on the adhesion layer 133. The layer of thermalinterface 110 can be formed of a thickness that is suitable for thethermal requirements of the IC package. That is, it can be thicker forhigher heat dissipation requirements, or thinner for less demanding heatdissipation requirements. The thickness of thermal interface 110 can be,for example, 500 microns for high heat dissipation or 75 microns forlower heat dissipation.

[0071] To provide a suitable solderable surface on the lower surface ofthermal interface 110, one or more additional adhesion layers 134-136are added.

[0072] In one embodiment, a layer 134 of titanium is first applied tothermal interface layer 110.

[0073] Next a layer 135 of nickel-vanadium is formed on layer 134.Either platinum or chromium could be substituted for nickel-vanadium.

[0074] Finally a layer 136 of gold is formed on layer 135. Nickel couldbe substituted for gold.

[0075] In addition, one or more adhesion layers 141-143 can be formed onthe upper surface 57 of die 40 in order to provide a suitable materialfor the lower-most adhesion layer 136 of IHS 120 to attach to.

[0076] In one embodiment, a layer 141 of titanium is formed on the uppersurface 57 of die 40.

[0077] Next a layer 142 of nickel-vanadium is formed on layer 141.Either platinum or chromium could be substituted for nickel-vanadium.

[0078] Finally a layer 143 of gold is formed on layer 142. Nickel couldbe substituted for gold.

[0079] Prior to undergoing solder reflow, a suitable flux and solderpaste are applied to one or both of layers 136 and 143, and IHS 120 ismoved in the direction indicated by arrows 117, so that layer 136 comesinto contact with layer 143.

[0080] In one embodiment, the titanium layers are approximately 200-500Angstroms (A) in thickness; the nickel-vanadium layers are approximately3500 Å; and the gold layers are approximately 1000 Å.

[0081]FIG. 6 illustrates a cross-sectional representation of a highcapacity thermal interface 111 to be affixed to an IHS 120, inaccordance with another embodiment of the invention.

[0082] As mentioned earlier, the thermal interface 111 can be formedapart from IHS 120 and subsequently affixed to the lower surface 58 oflid 122 of IHS 120, as will now be explained regarding FIGS. 6 and 7.

[0083] An amorphous or polycrystalline diamond layer 111 can be grown byany suitable method. The thickness of layer 111 can vary depending uponthe thermal requirements of the IC package. In one embodiment, layer 111is several hundred microns thick; however, the invention is not limitedto any particular thickness.

[0084] To facilitate affixing the thermal interface layer 111 to theunder surface 58 of IHS 120, one or more adhesion layers 121 of suitablematerial can be formed on the under side 58 of lid 122. In addition, oneor more adhesion layers 151-153 of suitable material can be formed onthe upper surface of thermal interface layer 111. In addition, one ormore adhesion layers 154-156 of suitable material can be formed on thelower surface of thermal interface layer 111 to provide a suitablebonding platform for a connection with the upper surface of die 40 (FIG.5).

[0085] Adhesion layers 121 and 151-156 can comprise metal from a groupthat includes chromium, gold, nickel, platinum, silver, titanium,tungsten, and vanadium, or alloys thereof. In one embodiment, layers 151and 154 comprise titanium; layers 152 and 155 comprise nickel-vanadium;and layers 121, 153, and 156 comprise gold. However, as mentioned aboveregarding FIG. 5, other materials could be substituted for theseparticular substances.

[0086] Prior to undergoing solder reflow, a suitable flux and solderpaste are applied to one or both of layers 121 and 153, and thermalinterface layer 111 is moved in the direction indicated by arrows 118,so that layer 153 comes into contact with layer 121.

[0087] While in the embodiments illustrated in FIGS. 5 and 6, thermalinterface 110 is described as being affixed to IHS 120 and to die 40through the use of solder, other attachment techniques could also beused.

[0088] The above-described composition, dimensions, number, and order oflayers are merely exemplary of the embodiments illustrated, and they arenot meant to be limiting.

[0089]FIG. 7 is a view of a wafer 140 of diamond thermal interfacematerial, which has been grown separate from an IHS, and a segment 145thereof prior to attachment to an IHS, in accordance with anotherembodiment of the invention.

[0090] The thermal interface 111 described in FIG. 6, including anyadhesion layers 151-156, will typically be formed in a large wafer 140comprising a plurality of individual thermally conductive elements 144.These elements can be separated from wafer 140. For example, element 145has been separated from wafer 140.

[0091]FIG. 8 is a flow diagram of a method of fabricating an IC package,in accordance with one embodiment of the invention. The method begins at300.

[0092] In 302, a layer of thermally conductive material is affixed tothe lower surface (e.g. 58, FIG. 3) of an integrated heat spreader (IHS)(e.g. 120, FIG. 3). For further details concerning this operation, referto FIG. 9 and its description below.

[0093] In 320, at least one die (e.g. 40, FIG. 3) is mounted on asubstrate (e.g. 50, FIG. 3), so that electrical contacts on a lowersurface of the die are coupled to corresponding contacts (e.g. 52, FIG.3) on the upper surface (e.g. 56, FIG. 3) of the substrate.

[0094] In 322, the IHS is mounted over at least one die so that thethermally conductive material is in contact with an upper surface of thedie.

[0095] In 324, the IHS wall (e.g. 124, FIG. 3) is coupled to the uppersurface of the substrate with a thermally conductive material (e.g. 66,FIG. 3).

[0096] A suitable process for performing 322 and 324 will now bedescribed with reference to FIG. 3. Solder paste is first applied to theback side of the die 40. Alternatively, the solder paste could beapplied to the surface of the thermally conductive element 110 thatfaces the back side of the die. Then a suitable sealant 66 is applied tothe OLGA substrate 50 where the periphery or boundary of IHS 120 willmake contact when it is positioned over the die 40.

[0097] Next, the IHS 120 is aligned, and an appropriate force can beapplied, for example using a spring, to hold IHS 120 in position. Thepackage is then put into a suitable heating environment, such as a flowfurnace, for solder reflow. Following solder join of the thermalinterface, the sealant at the IHS boundary is cured in a conventionaloven. Post cure, the securing spring is removed.

[0098] The method illustrated in FIG. 8 ends at 326.

[0099]FIG. 9 is a flow diagram of two alternative methods of affixing alayer of thermally conductive material to an integrated heat spreader(IHS). FIG. 9 elaborates upon 302 of FIG. 8.

[0100] In 304, a determination is made whether a layer of thermallyconductive material is to be grown on the lower surface of the IHS. Ifyes, the method proceeds to 306; otherwise, it proceeds to 310.

[0101] In 306, an adhesion layer (e.g. one or more layers 131-133, FIG.5) is formed on the IHS surface.

[0102] In 308, a layer of thermally conductive material (e.g. 110, FIG.5) is grown on the adhesion layer of the IHS surface. The material isfrom the group consisting of diamond, a diamond composite, and graphite.

[0103] In 310, a layer of thermally conductive material (e.g. 111, FIG.5) is grown apart from the IHS surface. The material is from the groupconsisting of diamond, a diamond composite, and graphite. The layer canbe grown in the form of a wafer (140, FIG. 7).

[0104] In 312, an adhesion layer (e.g. one or more layers 151-156, FIG.6) is formed on at least one surface of the layer of thermallyconductive material.

[0105] In 314, individual thermally conductive elements (e.g. 145, FIG.7) are separated from the grown layer.

[0106] In 316, individual thermally conductive elements are secured tothe under side of each IHS (e.g. 120, FIG. 6). The methods end at 318.

[0107] The operations described above with respect to the methodsillustrated in FIGS. 8 and 9 can be performed in a different order fromthose described herein.

[0108] The above-described choice of materials; geometry; number, order,dimensions, and composition of layers; mechanisms for affixing; andassembly sequencing can all be varied by one of ordinary skill in theart to optimize the thermal performance of the package.

[0109] Any suitable method, or combination of different methods, fordepositing the metal layers can be used, such as plating, sputtering,vapor, electrical, screening, stenciling, chemical including chemicalvapor deposition (CVD), vacuum, and so forth.

[0110] Before deposition of the one or more metal layers, the surface ofthe die can be prepared with a sputter etch, if desired, to improve theadhesion of the adhesion layer to the die surface; however, a sputteretch is not essential. Nor is the condition of the wafer surfaceessential. The wafer surface can be in unpolished, polished, orback-ground form.

[0111] The particular implementation of the IC package is very flexiblein terms of the orientation, size, number, order, and composition of itsconstituent elements. Various embodiments of the invention can beimplemented using various combinations of substrate technology, IHStechnology, high capacity thermal interface material, adhesionmaterials, and sealant to achieve the advantages of the presentinvention. The structure, including types of materials used, dimensions,layout, geometry, and so forth, of the IC package can be built in a widevariety of embodiments, depending upon the requirements of theelectronic assembly of which it forms a part.

[0112] FIGS. 3-7 are merely representational and are not drawn to scale.Certain proportions thereof may be exaggerated, while others may beminimized. FIGS. 3-7 are intended to illustrate various implementationsof the invention that can be understood and appropriately carried out bythose of ordinary skill in the art.

Conclusion

[0113] The present invention provides for an electronic assembly andmethods of manufacture thereof that minimize thermal dissipationproblems associated with high power delivery. An electronic systemand/or data processing system that incorporates one or more electronicassemblies that utilize the present invention can handle the relativelyhigh power densities associated with high performance integratedcircuits, and such systems are therefore more commercially attractive.

[0114] By substantially increasing the thermal dissipation from highperformance electronic assemblies, such electronic equipment can beoperated at increased clock frequencies. Alternatively, such equipmentcan be operated at reduced clock frequencies but with lower operatingtemperatures for increased reliability.

[0115] As shown herein, the present invention can be implemented in anumber of different embodiments, including a heat-dissipating structure,an integrated circuit package, an electronic assembly, an electronicsystem in the form of a data processing system, and various methods offabricating an IC package. Other embodiments will be readily apparent tothose of ordinary skill in the art. The elements, materials, geometries,dimensions, and sequence of operations can all be varied to suitparticular packaging requirements.

[0116] While certain operations have been described herein relative to“upper” and “lower” surfaces, it will be understood that thesedescriptors are relative, and that they would be reversed if the ICpackage were inverted. Therefore, these terms are not intended to belimiting.

[0117] Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. Therefore, it is manifestly intended that this invention belimited only by the claims and the equivalents thereof.

What is claimed is:
 1. A heat-dissipating structure for an integratedcircuit die comprising: a lid; a wall coupled to the lid and comprisinga surface to couple to a substrate; a thermally conductive elementcomprising a first surface coupled to the lid and a second surface tocouple to an integrated circuit die, the thermally conductive elementbeing from the group consisting of diamond, a diamond composite, andgraphite.
 2. The heat-dissipating structure recited in claim 1 andfurther comprising: an adhesion layer between the lid and the thermallyconductive element.
 3. The heat-dissipating structure recited in claim 2wherein the adhesion layer is formed of material from the groupconsisting of chromium, gold, nickel, platinum, silver, titanium,tungsten, and vanadium.
 4. The heat-dissipating structure recited inclaim 1 wherein the thermally conductive element comprises at least onesolderable layer.
 5. The heat-dissipating structure recited in claim 4wherein the at least one solderable layer is formed of material from thegroup consisting of chromium, gold, nickel, platinum, silver, titanium,tungsten, and vanadium.
 6. The heat-dissipating structure recited inclaim 1 wherein the thermally conductive element has a surface area thatis substantially the same as a surface area of the lid.
 7. Theheat-dissipating structure recited in claim 1 wherein the thermallyconductive element contacts the wall.
 8. An integrated circuit packagecomprising: a substrate; at least one die positioned on a surface of thesubstrate; a lid positioned over the at least one die; a wall coupled tothe lid and comprising a surface coupled to the substrate; and athermally conductive element coupled between the lid and the at leastone die, the thermally conductive element comprising a material from thegroup consisting of diamond, a diamond composite, and graphite.
 9. Theintegrated circuit package recited in claim 8 and further comprising: anadhesion layer between the lid and the thermally conductive element. 10.The integrated circuit package recited in claim 9 wherein the adhesionlayer is formed of material from the group consisting of chromium, gold,nickel, platinum, silver, titanium, tungsten, and vanadium.
 11. Theintegrated circuit package recited in claim 8 wherein the thermallyconductive element comprises at least one solderable layer.
 12. Theintegrated circuit package recited in claim 11 wherein the at least onesolderable layer is formed of material from the group consisting ofchromium, gold, nickel, platinum, silver, titanium, tungsten, andvanadium.
 13. The integrated circuit package recited in claim 8 whereinthe thermally conductive element has a surface area that issubstantially the same as a surface area of the lid.
 14. The integratedcircuit package recited in claim 8 wherein the thermally conductiveelement contacts the wall.
 15. The integrated circuit package recited inclaim 8 wherein the substrate is an organic substrate and wherein the atleast one die is positioned on the substrate through a land grid array.16. An electronic assembly comprising: at least one integrated circuitpackage comprising: a substrate; at least one die positioned on asurface of the substrate; a lid positioned over the at least one die; awall coupled to the lid and comprising a surface coupled to thesubstrate; and a thermally conductive element coupled between the lidand the at least one die, the thermally conductive element comprising amaterial from the group consisting of diamond, a diamond composite, andgraphite.
 17. The electronic assembly recited in claim 16 and furthercomprising: an adhesion layer between the lid and the thermallyconductive element.
 18. The integrated circuit package recited in claim17 wherein the adhesion layer is formed of material from the groupconsisting of chromium, gold, nickel, platinum, silver, titanium,tungsten, and vanadium.
 19. The integrated circuit package recited inclaim 16 wherein the thermally conductive element has a surface areathat is substantially the same as a surface area of the lid.
 20. Theintegrated circuit package recited in claim 16 wherein the thermallyconductive element contacts the wall.
 21. A data processing systemcomprising: a bus coupling components in the data processing system; adisplay coupled to the bus; external memory coupled to the bus; and aprocessor coupled to the bus and comprising an electronic assemblyincluding at least one integrated circuit package comprising: asubstrate; at least one die positioned on a surface of the substrate; alid positioned over the at least one die; a wall coupled to the lid andcomprising a surface coupled to the substrate; and a thermallyconductive element coupled between the lid and the at least one die, thethermally conductive element comprising a material from the groupconsisting of diamond, a diamond composite, and graphite.
 22. The dataprocessing system recited in claim 21 and further comprising: anadhesion layer between the lid and the thermally conductive element. 23.The integrated circuit package recited in claim 21 wherein the thermallyconductive element has a surface area that is substantially the same asa surface area of the lid, and wherein the thermally conductive elementcontacts the wall.
 24. A method of fabricating an integrated circuitpackage, the method comprising: affixing a layer of thermally conductivematerial to a lower surface of an integrated heat spreader (IHS), thematerial being from the group consisting of diamond, a diamondcomposite, and graphite; mounting a die on a substrate, so thatelectrical contacts on a lower surface of the die are coupled toelectrical contacts on an upper surface of the substrate; and mountingthe IHS over the die so that the thermally conductive material is incontact with the upper surface of the die.
 25. The method recited inclaim 24 wherein affixing comprises: growing the layer of thermallyconductive material on the IHS surface.
 26. The method recited in claim25 and further comprising: forming a layer of metal on the IHS surface,the layer of metal being from the group consisting of chromium, gold,nickel, platinum, silver, titanium, tungsten, and vanadium.
 27. Themethod recited in claim 24 and further comprising: growing the layer ofthermally conductive material apart from the IHS surface.
 28. The methodrecited in claim 27 and further comprising: forming a layer of metal onat least one surface of the layer of thermally conductive material, thelayer of metal being from the group consisting of titanium and tungsten.29. The method recited in claim 24 wherein the IHS comprises a wall, themethod further comprising: coupling the IHS wall to the upper surface ofthe substrate.
 30. The method recited in claim 29 wherein the IHS wallis coupled to the upper surface of the substrate with a thermallyconductive material.